CoAsia Semi (CEO DS Shin) unveiled its proprietary chiplet-based platform, CoCs™ (CoAsia Chiplet Solution), for the first time at “Arm Unlocked Seoul 2025” held on October 21.

Organized by British semiconductor company Arm, Arm Unlocked Seoul 2025 is a premier technology leadership summit designed to share the latest innovations and future trends in AI computing—from cloud to edge—based on Arm’s platform. The event gathered around 500 participants, including industry leaders and representatives from major global tech firms such as Samsung, Cadence, and Synopsys.
 

Representing CoAsia’s system semiconductor business, CoAsia Semi and CoAsia Nexell jointly showcased their next-generation chiplet platform CoCs™ at the event. Dae Hyup Ko, CEO of CoAsia Nexell, delivered a keynote presentation titled “Driving Chiplet Interoperability: Standards-Based System Design.”
 

Ko noted, “With the rapid expansion of AI and high-performance computing (HPC), system complexity is increasing as performance demands grow. As process nodes shrink, issues such as leakage, heat, and cost escalate—making the traditional Moore’s Law approach of merely packing more transistors no longer sustainable. The industry needs new alternatives that balance diverse power and performance requirements.”
 

In response to this evolving landscape, CoAsia Semi, as an Arm Total Design official partner, leverages Arm Neoverse V3 architecture to help customers accelerate SoC implementation for AI and HPC applications without complex development processes. The newly introduced CoCs™ chiplet architecture platform offers a scalable and cost-efficient alternative that enhances design flexibility and performance while reducing development time—addressing the growing need for high-performance, low-power solutions in AI computing.
 

Ko explained that CoCs™ integrates functionally separated dies into a unified system, enabling modular configurations tailored to specific performance needs. By implementing Arm Neoverse V3’s server-grade scalability through CoCs™ chiplet modularization, the platform achieves an optimal balance of performance, power, and area (PPA)—allowing for fast and reliable realization of customized AI/HPC SoCs and significantly shortening time-to-market.
 

Using a pre-verified Arm Neoverse V3 Compute Subsystem (CSS) minimizes design-stage risks, while iterative optimization during physical implementation improves power efficiency and die area utilization. Furthermore, a standardized chiplet interface software stack strengthens interoperability between chiplets.
 

DS Shin, CEO of CoAsia Semi and Head of CoAsia Group’s Semiconductor Division, stated, “We are reinforcing our end-to-end integrated support services covering everything from design and packaging to testing, mass production, and supply chain management for custom chiplet SoCs. CoCs™ effectively addresses interconnect reliability and yield management challenges in multi-die environments, enabling customers to shorten their design and development cycles and secure differentiated competitiveness.”